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Commit d337648b authored by Emilien WOLFF's avatar Emilien WOLFF
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controlUnit_complete

parent efc4fa40
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...@@ -54,39 +54,57 @@ begin ...@@ -54,39 +54,57 @@ begin
-- Process to describe the state register -- Process to describe the state register
-- Current state is provide at the output of the register -- Current state is provide at the output of the register
-- and is updated with the next state at each rising edge of clock -- and is updated with the next state at each rising edge of clock
process (_BLANK_) is process (I_clock,I_reset) is
begin begin
if I_reset = '1' then -- asynchronous reset (active high) if I_reset = '1' then -- asynchronous reset (active high)
SR_currentState <= _BLANK_ SR_currentState <= WAIT_SAMPLE ;
elsif rising_edge(I_clock) then -- rising clock edge elsif rising_edge(I_clock) then -- rising clock edge
_BLANK_ SR_currentState <= SR_nextState ;-- état futur dans été présent
end if; end if;
end process; end process;
-- Combinatorial process computing the next state which depends on -- Combinatorial process computing the next state which depends on
-- the current state and on the inputs -- the current state and on the inputs
process (_BLANK_) is process (SR_currentState,I_processingDone,I_inputSampleValid) is
begin begin
case SR_currentState is case SR_currentState is
when WAIT_SAMPLE => when WAIT_SAMPLE =>
_BLANK_ if I_inputSampleValid = '1' then
SR_nextState <= STORE;
when others => null;
else
SR_nextState <= WAIT_SAMPLE;
end if;
when STORE =>
SR_nextState <= PROCESSING_LOOP;
when OUTPUT =>
SR_nextState <= WAIT_END_SAMPLE;
when WAIT_END_SAMPLE =>
if I_inputSampleValid = '0' then
SR_nextState <= WAIT_SAMPLE;
else
SR_nextState <= WAIT_END_SAMPLE;
end if;
when others =>
SR_nextState <= WAIT_SAMPLE;
end case; end case;
end process; end process;
-- Rules to compute the outputs depending on the current state -- Rules to compute the outputs depending on the current state
-- (and on the inputs, if you want a Mealy machine). -- (and on the inputs, if you want a Mealy machine).
O_loadShift <= '1' when _BLANK_ else '0'; O_loadShift <= '1' when SR_currentState = STORE else '0';
O_initAddress <= '1' when _BLANK_ else '0'; O_initAddress <= '1' when SR_currentState = STORE else '0';
O_incrAddress <= '1' when _BLANK_ else '0'; O_incrAddress <= '1' when SR_currentState = PROCESSING_LOOP else '0';
O_initSum <= '1' when _BLANK_ else '0'; O_initSum <= '1' when SR_currentState = STORE else '0';
O_loadSum <= '1' when _BLANK_ else '0'; O_loadSum <= '1' when SR_currentState = PROCESSING_LOOP else '0';
O_loadOutput <= '1' when _BLANK_ else '0'; O_loadOutput <= '1' when SR_currentState = OUTPUT else '0';
O_FilteredSampleValid <= '1' when _BLANK_ else '0'; O_FilteredSampleValid <= '1' when SR_currentState = OUTPUT else '0';
......
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