Fin du tp

afa3809c · Francois-Xavier · 3ccbf5c4 · afa3809c · afa3809c · afa3809c
Commit afa3809c authored 1 month ago by Francois-Xavier
--- a/DEADJOE
+++ b/DEADJOE
--- a/src/hdl/module_D.vhd
+++ b/src/hdl/module_D.vhd
@@ -13,7 +13,7 @@ entity module_D is
    port (
        I_clk      : in  std_logic;
        I_rst      : in  std_logic;
-        I_addr     : in  std_logic_vector(integer(ceil(log2(real(natural(floor(G_fs/(4.0*G_f0))))))) - 2 downto 0);
+        I_addr     : in  std_logic_vector (integer(ceil(log2(real(natural(floor(G_fs/(4.0*G_f0))))))) - 1 downto 0);
        O_triangle : out std_logic_vector(G_N-1 downto 0)
        );
 end module_D;

--- a/src/hdl/tb_module_D.vhd
+++ b/src/hdl/tb_module_D.vhd
@@ -19,7 +19,7 @@ architecture behavior of tb_module_D is
        port (
            I_clk      : in  std_logic;
            I_rst      : in  std_logic;
-            I_addr     : in  std_logic_vector(integer(ceil(log2(real(natural(floor(G_fs/(4.0*G_f0))))))) - 1 downto 0);
+            I_addr     : in  std_logic_vector(integer(ceil(log2(real(natural(floor(C_fs/(4.0*C_f0))))))) - 1 downto 0); -- 5 bits
            O_triangle : out std_logic_vector(G_N-1 downto 0)
            );
    end component;

--- a/src/hdl/wave_generator.vhd
+++ b/src/hdl/wave_generator.vhd
@@ -96,7 +96,7 @@ begin
        port map (
            I_clk      => I_clk,
            I_rst      => I_rst,
-            I_addr     => S_addr,
+            I_addr     => S_addr(C_addr_half_w-1 downto 0),
            O_triangle => S_triangle_out_lut 
            );
@@ -121,7 +121,7 @@ begin
        port map (
            I_sel  => I_wave_sel,
            I_din0 => S_sine_out_lut,
-            I_din1 => S_wave_value ,
+            I_din1 => S_square ,
            I_din2 => S_saw_tooth_out_lut,
            I_din3 => S_triangle_out_lut,
            O_dout => S_wave_sample 
@@ -143,7 +143,7 @@ begin
            I_sel  => S_sign_sel,
            I_din0 => S_wave_sample,
            I_din1 => S_opposite_wave_sample,
-            O_dout => S_square 
+            O_dout => S_wave_value 
            );
    -- Module I
@@ -154,7 +154,7 @@ begin
        port map (
            I_clk  => I_clk,
            I_rst  => I_rst,
-            I_din  => S_square ,
+            I_din  => S_wave_value ,
            O_dout => O_wav
            );

--- a/vivado.jou
+++ b/vivado.jou
@@ -3,8 +3,8 @@
 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
 # IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
 # SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
-# Start of session at: Mon May  5 08:22:31 2025
+# Start of session at: Fri May  9 08:24:05 2025
-# Process ID: 8865
+# Process ID: 9584
 # Current directory: /homes/f24collo/tp-synthe-etudiant-f24collo
 # Command line: vivado
 # Log file: /homes/f24collo/tp-synthe-etudiant-f24collo/vivado.log
@@ -13,127 +13,42 @@
 # Platform          :Ubuntu
 # Operating System  :Ubuntu 24.04.2 LTS
 # Processor Detail  :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
-# CPU Frequency     :4388.250 MHz
+# CPU Frequency     :4398.212 MHz
 # CPU Physical cores:6
 # CPU Logical cores :12
 # Host memory       :16533 MB
 # Swap memory       :4294 MB
 # Total Virtual     :20828 MB
-# Available Virtual :17967 MB
+# Available Virtual :17043 MB
 #-----------------------------------------------------------
 start_gui
-ls
+open_project /homes/f24collo/tp-synthe-etudiant-f24collo/proj/Synthe.xpr
-cd ./tp-synthe-etudiant-f24collo
-ls
-cd proj
-source ./create_project.tcl
 update_compile_order -fileset sources_1
-# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+reset_run synth_1
-set_property source_mgmt_mode None [current_project]
-set_property top module_B [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-set_property top_arch behavioral [get_filesets sim_1]
-set_property top_file /homes/f24collo/tp-synthe-etudiant-f24collo/src/hdl/module_B.vhd [get_filesets sim_1]
-# Re-enabling previously disabled source management mode.
-set_property source_mgmt_mode All [current_project]
-launch_simulation
-source module_B.tcl
-# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
-set_property source_mgmt_mode None [current_project]
-set_property top tb_module_B [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-# Re-enabling previously disabled source management mode.
-set_property source_mgmt_mode All [current_project]
-launch_simulation
-source tb_module_B.tcl
-add_bp {/homes/f24collo/tp-synthe-etudiant-f24collo/src/hdl/tb_module_B.vhd} 59
-remove_bps -file {/homes/f24collo/tp-synthe-etudiant-f24collo/src/hdl/tb_module_B.vhd} -line 59
-# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
-set_property source_mgmt_mode None [current_project]
-set_property top tb_module_C [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-# Re-enabling previously disabled source management mode.
-set_property source_mgmt_mode All [current_project]
-launch_simulation
-source tb_module_C.tcl
-close_sim
-launch_simulation
-source tb_module_C.tcl
-# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
-set_property source_mgmt_mode None [current_project]
-set_property top tb_module_D [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-# Re-enabling previously disabled source management mode.
-set_property source_mgmt_mode All [current_project]
-launch_simulation
-source tb_module_D.tcl
-# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
-set_property source_mgmt_mode None [current_project]
-set_property top tb_module_E [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-# Re-enabling previously disabled source management mode.
-set_property source_mgmt_mode All [current_project]
-launch_simulation
-source tb_module_E.tcl
-# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
-set_property source_mgmt_mode None [current_project]
-set_property top tb_module_F [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-# Re-enabling previously disabled source management mode.
-set_property source_mgmt_mode All [current_project]
-launch_simulation
-source tb_module_F.tcl
-# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
-set_property source_mgmt_mode None [current_project]
-set_property top tb_module_G [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-# Re-enabling previously disabled source management mode.
-set_property source_mgmt_mode All [current_project]
-launch_simulation
-source tb_module_G.tcl
-# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
-set_property source_mgmt_mode None [current_project]
-set_property top tb_module_H [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-# Re-enabling previously disabled source management mode.
-set_property source_mgmt_mode All [current_project]
-launch_simulation
-source tb_module_H.tcl
-# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
-set_property source_mgmt_mode None [current_project]
-set_property top tb_module_I [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-# Re-enabling previously disabled source management mode.
-set_property source_mgmt_mode All [current_project]
-launch_simulation
-source tb_module_I.tcl
-# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
-set_property source_mgmt_mode None [current_project]
-set_property top tb_module_G [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
-# Re-enabling previously disabled source management mode.
-set_property source_mgmt_mode All [current_project]
-current_sim simulation_8
-close_sim
-launch_simulation
-source tb_module_G.tcl
 launch_runs synth_1 -jobs 6
 wait_on_run synth_1
-# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+reset_run synth_1
-set_property source_mgmt_mode None [current_project]
+launch_runs synth_1 -jobs 6
-set_property top tb_module_B [get_filesets sim_1]
+wait_on_run synth_1
-set_property top_lib xil_defaultlib [get_filesets sim_1]
+reset_run synth_1
-# Re-enabling previously disabled source management mode.
+launch_runs synth_1 -jobs 6
-set_property source_mgmt_mode All [current_project]
+wait_on_run synth_1
-current_sim simulation_4
+reset_run synth_1
-current_sim simulation_11
+launch_runs synth_1 -jobs 6
-close_sim
+wait_on_run synth_1
-current_sim simulation_10
+reset_run synth_1
-close_sim
+launch_runs synth_1 -jobs 6
-save_wave_config {/homes/f24collo/tp-synthe-etudiant-f24collo/proj/tb_module_H_behav.wcfg}
+wait_on_run synth_1
-current_sim simulation_9
+reset_run synth_1
-close_sim
+launch_runs synth_1 -jobs 6
-current_sim simulation_7
+wait_on_run synth_1
-close_sim
+reset_run synth_1
-current_sim simulation_6
+launch_runs synth_1 -jobs 6
-close_sim
+wait_on_run synth_1
+reset_run synth_1
+launch_runs impl_1 -to_step write_bitstream -jobs 12
+wait_on_run impl_1
+reset_run synth_1
+launch_runs impl_1 -to_step write_bitstream -jobs 12
+wait_on_run impl_1
+open_run impl_1
--- a/vivado.log
+++ b/vivado.log
--- a/vivado_5844.backup.jou
+++ b/vivado_5844.backup.jou
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Fri May  9 08:06:38 2025
+# Process ID: 5844
+# Current directory: /homes/f24collo/tp-synthe-etudiant-f24collo
+# Command line: vivado
+# Log file: /homes/f24collo/tp-synthe-etudiant-f24collo/vivado.log
+# Journal file: /homes/f24collo/tp-synthe-etudiant-f24collo/vivado.jou
+# Running On        :fl-tp-br-515
+# Platform          :Ubuntu
+# Operating System  :Ubuntu 24.04.2 LTS
+# Processor Detail  :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency     :4334.306 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory       :16533 MB
+# Swap memory       :4294 MB
+# Total Virtual     :20828 MB
+# Available Virtual :19347 MB
+#-----------------------------------------------------------
+start_gui
+open_project /homes/f24collo/tp-synthe-etudiant-f24collo/proj/Synthe.xpr
+update_compile_order -fileset sources_1
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+reset_run synth_1
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
--- a/vivado_5844.backup.log
+++ b/vivado_5844.backup.log
--- a/vivado_8865.backup.jou
+++ b/vivado_8865.backup.jou
+#-----------------------------------------------------------
+# Vivado v2024.1 (64-bit)
+# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
+# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
+# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
+# Start of session at: Mon May  5 08:22:31 2025
+# Process ID: 8865
+# Current directory: /homes/f24collo/tp-synthe-etudiant-f24collo
+# Command line: vivado
+# Log file: /homes/f24collo/tp-synthe-etudiant-f24collo/vivado.log
+# Journal file: /homes/f24collo/tp-synthe-etudiant-f24collo/vivado.jou
+# Running On        :fl-tp-br-515
+# Platform          :Ubuntu
+# Operating System  :Ubuntu 24.04.2 LTS
+# Processor Detail  :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
+# CPU Frequency     :4388.250 MHz
+# CPU Physical cores:6
+# CPU Logical cores :12
+# Host memory       :16533 MB
+# Swap memory       :4294 MB
+# Total Virtual     :20828 MB
+# Available Virtual :17967 MB
+#-----------------------------------------------------------
+start_gui
+ls
+cd ./tp-synthe-etudiant-f24collo
+ls
+cd proj
+source ./create_project.tcl
+update_compile_order -fileset sources_1
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top module_B [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+set_property top_arch behavioral [get_filesets sim_1]
+set_property top_file /homes/f24collo/tp-synthe-etudiant-f24collo/src/hdl/module_B.vhd [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source module_B.tcl
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_B [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_B.tcl
+add_bp {/homes/f24collo/tp-synthe-etudiant-f24collo/src/hdl/tb_module_B.vhd} 59
+remove_bps -file {/homes/f24collo/tp-synthe-etudiant-f24collo/src/hdl/tb_module_B.vhd} -line 59
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_C [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_C.tcl
+close_sim
+launch_simulation
+source tb_module_C.tcl
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_D [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_D.tcl
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_E [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_E.tcl
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_F [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_F.tcl
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_G [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_G.tcl
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_H [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_H.tcl
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_I [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+launch_simulation
+source tb_module_I.tcl
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_G [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+current_sim simulation_8
+close_sim
+launch_simulation
+source tb_module_G.tcl
+launch_runs synth_1 -jobs 6
+wait_on_run synth_1
+# Disabling source management mode.  This is to allow the top design properties to be set without GUI intervention.
+set_property source_mgmt_mode None [current_project]
+set_property top tb_module_B [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+# Re-enabling previously disabled source management mode.
+set_property source_mgmt_mode All [current_project]
+current_sim simulation_4
+current_sim simulation_11
+close_sim
+current_sim simulation_10
+close_sim
+save_wave_config {/homes/f24collo/tp-synthe-etudiant-f24collo/proj/tb_module_H_behav.wcfg}
+current_sim simulation_9
+close_sim
+current_sim simulation_7
+close_sim
+current_sim simulation_6
+close_sim
--- a/vivado_8865.backup.log
+++ b/vivado_8865.backup.log
--- a/vivado_pid5844.str
+++ b/vivado_pid5844.str
--- a/vivado_pid9584.str
+++ b/vivado_pid9584.str