feat

proj/project_1/project_1.cache/wt/xsim.wdf

 version:1
-7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
+7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00
 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
-eof:241934075
+eof:2427094519

proj/project_1/project_1.sim/sim_1/behav/xsim/compile.sh

@@ -6,7 +6,7 @@
 # Simulator   : AMD Vivado Simulator
 # Description : Script for compiling the simulation design source files
 #
-# Generated by Vivado on Wed Mar 19 12:10:31 CET 2025
+# Generated by Vivado on Wed Mar 19 12:17:57 CET 2025
 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
 #
 # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.log

@@ -5,4 +5,15 @@ Running: /opt/img/Vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr
 Using 8 slave threads.
 Starting static elaboration
 Completed static elaboration
-INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling architecture archi_operativeunit of entity xil_defaultlib.controlUnit [controlunit_default]
+Compiling architecture arch_operativeunit of entity xil_defaultlib.operativeUnit [operativeunit_default]
+Compiling architecture archi_firunit of entity xil_defaultlib.firUnit [firunit_default]
+Compiling architecture archi_tb_firunit of entity xil_defaultlib.tb_firunit
+Built simulation snapshot tb_firUnit_behav

proj/project_1/project_1.sim/sim_1/behav/xsim/elaborate.sh

@@ -6,7 +6,7 @@
 # Simulator   : AMD Vivado Simulator
 # Description : Script for elaborating the compiled design
 #
-# Generated by Vivado on Wed Mar 19 12:10:33 CET 2025
+# Generated by Vivado on Wed Mar 19 12:17:59 CET 2025
 # SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
 #
 # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsim.rlx

 
 { 
-    crc :  1677624650740528615  , 
+    crc :  1860796047234000762  , 
     ccp_crc :  0  , 
     cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_firUnit_behav xil_defaultlib.tb_firUnit" , 
     buildDate : "May 22 2024" , 

proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/tb_firUnit_behav/xsimkernel.log

-Running: xsim.dir/tb_firUnit_behav/xsimk -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 51971
+Running: xsim.dir/tb_firUnit_behav/xsimk -simmode gui -wdb tb_firUnit_behav.wdb -simrunnum 0 -socket 33467
 Design successfully loaded
 Design Loading Memory Usage: 20188 KB (Peak: 20752 KB)
 Design Loading CPU Usage: 20 ms

proj/project_1/project_1.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx

@@ -2,7 +2,7 @@
 2020.2
 May 22 2024
 18:54:44
-/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd,1742382607,vhdl,/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,controlunit,,,,,,,,
+/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/controlUnit.vhd,1742383073,vhdl,/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,controlunit,,,,,,,,
 /homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,1742373132,vhdl,/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd,,,firunit,,,,,,,,
 /homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/operativeUnit.vhd,1742376828,vhdl,/homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/firUnit.vhd,,,operativeunit,,,,,,,,
 /homes/a24perei/medcon/tp-ecg-etudiant-a24perei/src/hdl/tb_firUnit.vhd,1742373132,vhdl,,,,tb_firunit,,,,,,,,