Skip to content
Snippets Groups Projects
Commit 7b2773a0 authored by Michelly LUIS LACERDA's avatar Michelly LUIS LACERDA
Browse files

tp fini

parent 918b5c88
Branches
No related tags found
No related merge requests found
......@@ -36,6 +36,10 @@ begin
process (I_clk, I_rst)
begin
if(I_rst = '1')then
O_counting <= '0';
O_store <= '0';
O_l_red <= '0';
O_l_green <= '1';
SR_STATE <= st_wait_success;
elsif rising_edge(I_clk)then
......@@ -69,7 +73,7 @@ begin
if I_invalide = '0' then
SR_STATE <= st_store;
elsif I_invalide = '1' then
else
SR_STATE <= st_wait_failed;
end if;
......@@ -81,7 +85,7 @@ begin
if I_end = '1' then
SR_STATE <= st_end_red;
elsif I_end = '0' then
else
SR_STATE <= st_wait_success;
end if;
......@@ -105,7 +109,7 @@ begin
SR_STATE <= st_end_red;
end if;
when st_wait_failed =>
when others =>
O_counting <= '0';
O_store <= '0';
O_l_red <= '1';
......@@ -115,8 +119,6 @@ begin
SR_STATE <= st_counting;
end if;
when others =>
SR_STATE <= st_wait_success;
end case;
end if;
......
......@@ -20,12 +20,12 @@ architecture modulo4_a of compteur_modulo4 is
begin
mod4 : process (clk, rst)
mod4 : process (I_clk, I_rst)
begin
if rst = '1' then
if I_rst = '1' then
SR_Counter <= "00";
elsif rising_edge(clk) then
elsif rising_edge(I_clk) then
if SR_Counter = "11" then
SR_Counter <= "00";
else
......
......@@ -29,7 +29,7 @@ begin
if I_block = '0' then
SR_Counter <= SR_Counter + 1;
if SR_Counter = "111" then
if SR_Counter = "101" then
SR_Counter <= "000";
end if;
else
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment