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Commit f21852cc authored by BEAUMONT Leo's avatar BEAUMONT Leo
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Première sauvegarde, ajout du diagramme descriptif de l'ensemble des modules... 

Première sauvegarde, ajout du diagramme descriptif de l'ensemble des modules et connexion des cables dans le fichier wave_genrator.vhd
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docs/diagramme_complete.drawio 0 → 100644
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<mxfile host="app.diagrams.net" agent="Mozilla/5.0 (X11; Linux x86_64; rv:138.0) Gecko/20100101 Firefox/138.0" version="26.2.14">
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src/hdl/wave_generator.vhd
+ 30
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...@@ -64,12 +64,12 @@ begin ...@@ -64,12 +64,12 @@ begin
G_MAX_VAL => natural(floor(G_fs/(2.0*G_f0))) G_MAX_VAL => natural(floor(G_fs/(2.0*G_f0)))
) )
port map ( port map (
I_clk => , I_clk => I_clk,
I_rst => , I_rst => I_rst,
I_u_d => , I_u_d => S_u_d,
O_val => , O_val => S_addr,
O_last => , O_last => S_last,
O_middle => O_middle => S_middle
); );
-- Module C -- Module C
...@@ -94,10 +94,10 @@ begin ...@@ -94,10 +94,10 @@ begin
G_fs => G_fs G_fs => G_fs
) )
port map ( port map (
I_clk => , I_clk => I_clk,
I_rst => , I_rst => I_rst,
I_addr => , I_addr => S_addr,
O_triangle => O_triangle => S_triangle_out_lut
); );
-- Module E -- Module E
...@@ -108,10 +108,10 @@ begin ...@@ -108,10 +108,10 @@ begin
G_fs => G_fs G_fs => G_fs
) )
port map ( port map (
I_clk => , I_clk => I_clk,
I_rst => , I_rst => I_rst,
I_addr => , I_addr => S_addr,
O_saw_tooth => O_saw_tooth => S_saw_tooth_out_lut
); );
S_square <= ((G_N-1) => '0', others => '1'); S_square <= ((G_N-1) => '0', others => '1');
...@@ -119,12 +119,12 @@ begin ...@@ -119,12 +119,12 @@ begin
-- Module F -- Module F
F_inst : entity work.module_F F_inst : entity work.module_F
port map ( port map (
I_sel => , I_sel => I_wave_sel,
I_din0 => , I_din0 => S_sine_out_lut,
I_din1 => , I_din1 => S_square,
I_din2 => , I_din2 => S_saw_tooth_out_lut,
I_din3 => , I_din3 => S_triangle_out_lut,
O_dout => O_dout => S_wave_value
); );
-- Module G -- Module G
...@@ -133,17 +133,17 @@ begin ...@@ -133,17 +133,17 @@ begin
G_N => G_N G_N => G_N
) )
port map ( port map (
I_din => , I_din => S_wave_value,
O_dout => O_dout => S_opposite_wave_sample
); );
-- Module H -- Module H
H_inst : entity work.module_H H_inst : entity work.module_H
port map ( port map (
I_sel => , I_sel => S_sign_sel,
I_din0 => , I_din0 => S_wave_value,
I_din1 => , I_din1 => S_opposite_wave_sample,
O_dout => O_dout => S_wave_sample
); );
-- Module I -- Module I
...@@ -152,10 +152,10 @@ begin ...@@ -152,10 +152,10 @@ begin
G_N => G_N G_N => G_N
) )
port map ( port map (
I_clk => , I_clk => I_clk,
I_rst => , I_rst => I_rst,
I_din => , I_din => S_wave_sample,
O_dout => O_dout => O_wav
); );
end arch; end arch;
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#-----------------------------------------------------------
# Vivado v2024.1 (64-bit)
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
# Start of session at: Mon May 5 08:28:17 2025
# Process ID: 6316
# Current directory: /homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum
# Command line: vivado
# Log file: /homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/vivado.log
# Journal file: /homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/vivado.jou
# Running On :fl-tp-br-520
# Platform :Ubuntu
# Operating System :Ubuntu 24.04.2 LTS
# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
# CPU Frequency :4392.091 MHz
# CPU Physical cores:6
# CPU Logical cores :12
# Host memory :16533 MB
# Swap memory :4294 MB
# Total Virtual :20828 MB
# Available Virtual :18868 MB
#-----------------------------------------------------------
start_gui
cd tp-synthe-etudiant-l24beaum/proj
ls
pwd
cd proj
ls
source ./create_project.tcl
update_compile_order -fileset sources_1
launch_simulation
source tb_module_B.tcl
# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
set_property source_mgmt_mode None [current_project]
set_property top tb_module_C [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
# Re-enabling previously disabled source management mode.
set_property source_mgmt_mode All [current_project]
launch_simulation
source tb_module_C.tcl
current_sim simulation_1
close_sim
# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
set_property source_mgmt_mode None [current_project]
set_property top tb_module_D [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
# Re-enabling previously disabled source management mode.
set_property source_mgmt_mode All [current_project]
launch_simulation
source tb_module_D.tcl
# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
set_property source_mgmt_mode None [current_project]
set_property top tb_module_E [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
# Re-enabling previously disabled source management mode.
set_property source_mgmt_mode All [current_project]
launch_simulation
source tb_module_E.tcl
# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
set_property source_mgmt_mode None [current_project]
set_property top tb_module_F [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
# Re-enabling previously disabled source management mode.
set_property source_mgmt_mode All [current_project]
launch_simulation
source tb_module_F.tcl
current_sim simulation_2
close_sim
close_sim
close_sim
# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
set_property source_mgmt_mode None [current_project]
set_property top tb_wave_generator [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
# Re-enabling previously disabled source management mode.
set_property source_mgmt_mode All [current_project]
launch_simulation
launch_simulation
launch_runs synth_1 -jobs 6
wait_on_run synth_1
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vivado_pid6316.str 0 → 100644
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