Skip to content
Snippets Groups Projects
Commit f21852cc authored by BEAUMONT Leo's avatar BEAUMONT Leo
Browse files

Première sauvegarde, ajout du diagramme descriptif de l'ensemble des modules...

Première sauvegarde, ajout du diagramme descriptif de l'ensemble des modules et connexion des cables dans le fichier wave_genrator.vhd
parent 490d4bad
No related branches found
No related tags found
No related merge requests found
<mxfile host="app.diagrams.net" agent="Mozilla/5.0 (X11; Linux x86_64; rv:138.0) Gecko/20100101 Firefox/138.0" version="26.2.14">
<diagram name="Page-1" id="ZRCvXX_TBlFcA-i0oMmK">
<mxGraphModel dx="2462" dy="765" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="1169" pageHeight="827" math="0" shadow="0">
<root>
<mxCell id="0" />
<mxCell id="1" parent="0" />
<mxCell id="liv1zIGuVtiVySRaDl_v-15" value="" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#f5f5f5;fontColor=#333333;strokeColor=#666666;arcSize=3;" parent="1" vertex="1">
<mxGeometry y="40" width="1320" height="720" as="geometry" />
</mxCell>
<mxCell id="liv1zIGuVtiVySRaDl_v-1" value="&lt;div style=&quot;line-height: 50%;&quot;&gt;&lt;div&gt;A&lt;/div&gt;&lt;div&gt;&lt;font style=&quot;font-size: 14px; line-height: 50%;&quot;&gt;Circuit séquentiel&lt;/font&gt;&lt;/div&gt;&lt;div&gt;&lt;font style=&quot;font-size: 14px; line-height: 50%;&quot;&gt;Générateur de signal qui oscile cicliquement entre 4 valeur sur state_reg.&lt;/font&gt;&lt;/div&gt;&lt;/div&gt;" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#dae8fc;strokeColor=#6c8ebf;fontFamily=Ubuntu Mono;fontSize=40;" parent="1" vertex="1">
<mxGeometry x="160" y="80" width="280" height="160" as="geometry" />
</mxCell>
<mxCell id="liv1zIGuVtiVySRaDl_v-2" value="&lt;div style=&quot;line-height: 50%;&quot;&gt;&lt;div&gt;D&lt;/div&gt;&lt;div&gt;&lt;font style=&quot;font-size: 14px; line-height: 50%;&quot;&gt;Circuit séquentiel&lt;/font&gt;&lt;/div&gt;&lt;div&gt;&lt;font style=&quot;font-size: 14px; line-height: 50%;&quot;&gt;&amp;nbsp;&lt;/font&gt;&lt;font style=&quot;font-size: 14px; line-height: 50%;&quot;&gt;Tableau de valeurs (linéairement croissante) qui renvoi la valeur à l&#39;adresse demandée.&lt;/font&gt;&lt;/div&gt;&lt;/div&gt;" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#dae8fc;strokeColor=#6c8ebf;fontFamily=Ubuntu Mono;fontSize=40;" parent="1" vertex="1">
<mxGeometry x="160" y="320" width="280" height="160" as="geometry" />
</mxCell>
<mxCell id="liv1zIGuVtiVySRaDl_v-3" value="&lt;div style=&quot;line-height: 50%;&quot;&gt;&lt;div&gt;&lt;font style=&quot;line-height: 50%;&quot;&gt;B&lt;/font&gt;&lt;/div&gt;&lt;div&gt;&lt;font style=&quot;font-size: 14px; line-height: 50%;&quot;&gt;Circuit séquentiel&lt;/font&gt;&lt;/div&gt;&lt;div&gt;&lt;font style=&quot;font-size: 14px; line-height: 50%;&quot;&gt;Compteur/décompteur controlé par I_u_d avec des triggers sur des valeurs spécifiques de (SR_val_reg, I_u_d).&lt;/font&gt;&lt;/div&gt;&lt;/div&gt;" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#dae8fc;strokeColor=#6c8ebf;fontFamily=Ubuntu Mono;fontSize=40;" parent="1" vertex="1">
<mxGeometry x="520" y="80" width="280" height="160" as="geometry" />
</mxCell>
<mxCell id="liv1zIGuVtiVySRaDl_v-4" value="&lt;div style=&quot;line-height: 50%;&quot;&gt;&lt;div&gt;&lt;font&gt;I&lt;/font&gt;&lt;/div&gt;&lt;div&gt;&lt;font style=&quot;font-size: 13px;&quot;&gt;Circuit séquentiel&lt;/font&gt;&lt;/div&gt;&lt;div&gt;&lt;font style=&quot;font-size: 13px;&quot;&gt;Registre synchrone qui renvoi I_din sur O_dout au front montant de I_clk jusqu&#39;au prochain front montant.&lt;/font&gt;&lt;/div&gt;&lt;/div&gt;" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#dae8fc;strokeColor=#6c8ebf;fontFamily=Ubuntu Mono;fontSize=40;" parent="1" vertex="1">
<mxGeometry x="880" y="560" width="280" height="160" as="geometry" />
</mxCell>
<mxCell id="liv1zIGuVtiVySRaDl_v-5" value="&lt;div style=&quot;line-height: 50%;&quot;&gt;&lt;div&gt;&lt;font style=&quot;line-height: 50%;&quot;&gt;F&lt;/font&gt;&lt;/div&gt;&lt;div&gt;&lt;font style=&quot;font-size: 14px; line-height: 50%;&quot;&gt;Circuit combinatoire&lt;/font&gt;&lt;/div&gt;&lt;div&gt;&lt;font style=&quot;font-size: 14px; line-height: 50%;&quot;&gt;C&#39;est un multiplexer 4 entrées + entrée de sélection.&lt;/font&gt;&lt;/div&gt;&lt;/div&gt;" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#dae8fc;strokeColor=#6c8ebf;fontFamily=Ubuntu Mono;fontSize=40;" parent="1" vertex="1">
<mxGeometry x="880" y="320" width="280" height="160" as="geometry" />
</mxCell>
<mxCell id="liv1zIGuVtiVySRaDl_v-6" value="&lt;div style=&quot;line-height: 50%;&quot;&gt;&lt;div&gt;C&lt;/div&gt;&lt;div&gt;&lt;font style=&quot;font-size: 14px; line-height: 50%;&quot;&gt;Circuit séquentiel&lt;/font&gt;&lt;/div&gt;&lt;div&gt;&lt;font style=&quot;font-size: 14px; line-height: 50%;&quot;&gt;Tableau de valeurs (sinusoïdales) qui renvoi la valeur à l&#39;adresse demandée.&lt;/font&gt;&lt;/div&gt;&lt;/div&gt;" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#dae8fc;strokeColor=#6c8ebf;fontFamily=Ubuntu Mono;fontSize=40;" parent="1" vertex="1">
<mxGeometry x="880" y="80" width="280" height="160" as="geometry" />
</mxCell>
<mxCell id="liv1zIGuVtiVySRaDl_v-7" value="&lt;div style=&quot;line-height: 50%;&quot;&gt;&lt;div&gt;&lt;font style=&quot;line-height: 50%;&quot;&gt;G&lt;/font&gt;&lt;/div&gt;&lt;div&gt;&lt;font style=&quot;font-size: 14px; line-height: 50%;&quot;&gt;Circuit combinatoire&lt;/font&gt;&lt;/div&gt;&lt;div&gt;&lt;font style=&quot;font-size: 14px; line-height: 50%;&quot;&gt;Inverseur de signe de I_din sur O_dout.&lt;/font&gt;&lt;/div&gt;&lt;/div&gt;" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#dae8fc;strokeColor=#6c8ebf;fontFamily=Ubuntu Mono;fontSize=40;" parent="1" vertex="1">
<mxGeometry x="160" y="560" width="280" height="160" as="geometry" />
</mxCell>
<mxCell id="liv1zIGuVtiVySRaDl_v-8" value="&lt;div style=&quot;line-height: 50%;&quot;&gt;&lt;div&gt;H&lt;/div&gt;&lt;div&gt;&lt;font style=&quot;font-size: 14px; line-height: 50%;&quot;&gt;Circuit combinatoire&lt;/font&gt;&lt;/div&gt;&lt;div&gt;&lt;font style=&quot;font-size: 14px; line-height: 50%;&quot;&gt;C&#39;est un multiplexer 2 entrées + entrée de sélection.&lt;/font&gt;&lt;/div&gt;&lt;/div&gt;" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#dae8fc;strokeColor=#6c8ebf;fontFamily=Ubuntu Mono;fontSize=40;" parent="1" vertex="1">
<mxGeometry x="520" y="560" width="280" height="160" as="geometry" />
</mxCell>
<mxCell id="liv1zIGuVtiVySRaDl_v-9" value="&lt;div style=&quot;line-height: 50%;&quot;&gt;&lt;div&gt;E&lt;/div&gt;&lt;div&gt;&lt;font style=&quot;font-size: 14px; line-height: 50%;&quot;&gt;Circuit séquentiel&lt;/font&gt;&lt;/div&gt;&lt;div&gt;&lt;font style=&quot;font-size: 14px; line-height: 50%;&quot;&gt;&amp;nbsp;&lt;/font&gt;&lt;font style=&quot;font-size: 14px; line-height: 50%;&quot;&gt;Tableau de valeurs (dent de scie) qui renvoi la valeur à l&#39;adresse demandée.&lt;/font&gt;&lt;/div&gt;&lt;/div&gt;" style="rounded=1;whiteSpace=wrap;html=1;fillColor=#dae8fc;strokeColor=#6c8ebf;fontFamily=Ubuntu Mono;fontSize=40;" parent="1" vertex="1">
<mxGeometry x="520" y="320" width="280" height="160" as="geometry" />
</mxCell>
<mxCell id="liv1zIGuVtiVySRaDl_v-10" value="I_clk" style="shape=step;perimeter=stepPerimeter;whiteSpace=wrap;html=1;fixedSize=1;fillColor=#f0a30a;strokeColor=#BD7000;fontColor=#000000;fontFamily=Ubuntu Mono;fontSize=18;fontStyle=1" parent="1" vertex="1">
<mxGeometry x="-40" y="120" width="160" height="40" as="geometry" />
</mxCell>
<mxCell id="liv1zIGuVtiVySRaDl_v-11" value="I_rst" style="shape=step;perimeter=stepPerimeter;whiteSpace=wrap;html=1;fixedSize=1;fillColor=#f0a30a;strokeColor=#BD7000;fontColor=#000000;fontFamily=Ubuntu Mono;fontSize=18;fontStyle=1" parent="1" vertex="1">
<mxGeometry x="-40" y="200" width="160" height="40" as="geometry" />
</mxCell>
<mxCell id="liv1zIGuVtiVySRaDl_v-12" value="I_wave_sel" style="shape=step;perimeter=stepPerimeter;whiteSpace=wrap;html=1;fixedSize=1;fillColor=#f0a30a;strokeColor=#BD7000;fontColor=#000000;fontFamily=Ubuntu Mono;fontSize=18;fontStyle=1" parent="1" vertex="1">
<mxGeometry x="-40" y="280" width="160" height="40" as="geometry" />
</mxCell>
<mxCell id="liv1zIGuVtiVySRaDl_v-14" value="O_wav" style="shape=step;perimeter=stepPerimeter;whiteSpace=wrap;html=1;fixedSize=1;fillColor=#f0a30a;strokeColor=#BD7000;fontColor=#000000;fontFamily=Ubuntu Mono;fontSize=18;fontStyle=1" parent="1" vertex="1">
<mxGeometry x="1200" y="120" width="160" height="40" as="geometry" />
</mxCell>
</root>
</mxGraphModel>
</diagram>
</mxfile>
...@@ -64,12 +64,12 @@ begin ...@@ -64,12 +64,12 @@ begin
G_MAX_VAL => natural(floor(G_fs/(2.0*G_f0))) G_MAX_VAL => natural(floor(G_fs/(2.0*G_f0)))
) )
port map ( port map (
I_clk => , I_clk => I_clk,
I_rst => , I_rst => I_rst,
I_u_d => , I_u_d => S_u_d,
O_val => , O_val => S_addr,
O_last => , O_last => S_last,
O_middle => O_middle => S_middle
); );
-- Module C -- Module C
...@@ -94,10 +94,10 @@ begin ...@@ -94,10 +94,10 @@ begin
G_fs => G_fs G_fs => G_fs
) )
port map ( port map (
I_clk => , I_clk => I_clk,
I_rst => , I_rst => I_rst,
I_addr => , I_addr => S_addr,
O_triangle => O_triangle => S_triangle_out_lut
); );
-- Module E -- Module E
...@@ -108,10 +108,10 @@ begin ...@@ -108,10 +108,10 @@ begin
G_fs => G_fs G_fs => G_fs
) )
port map ( port map (
I_clk => , I_clk => I_clk,
I_rst => , I_rst => I_rst,
I_addr => , I_addr => S_addr,
O_saw_tooth => O_saw_tooth => S_saw_tooth_out_lut
); );
S_square <= ((G_N-1) => '0', others => '1'); S_square <= ((G_N-1) => '0', others => '1');
...@@ -119,12 +119,12 @@ begin ...@@ -119,12 +119,12 @@ begin
-- Module F -- Module F
F_inst : entity work.module_F F_inst : entity work.module_F
port map ( port map (
I_sel => , I_sel => I_wave_sel,
I_din0 => , I_din0 => S_sine_out_lut,
I_din1 => , I_din1 => S_square,
I_din2 => , I_din2 => S_saw_tooth_out_lut,
I_din3 => , I_din3 => S_triangle_out_lut,
O_dout => O_dout => S_wave_value
); );
-- Module G -- Module G
...@@ -133,17 +133,17 @@ begin ...@@ -133,17 +133,17 @@ begin
G_N => G_N G_N => G_N
) )
port map ( port map (
I_din => , I_din => S_wave_value,
O_dout => O_dout => S_opposite_wave_sample
); );
-- Module H -- Module H
H_inst : entity work.module_H H_inst : entity work.module_H
port map ( port map (
I_sel => , I_sel => S_sign_sel,
I_din0 => , I_din0 => S_wave_value,
I_din1 => , I_din1 => S_opposite_wave_sample,
O_dout => O_dout => S_wave_sample
); );
-- Module I -- Module I
...@@ -152,10 +152,10 @@ begin ...@@ -152,10 +152,10 @@ begin
G_N => G_N G_N => G_N
) )
port map ( port map (
I_clk => , I_clk => I_clk,
I_rst => , I_rst => I_rst,
I_din => , I_din => S_wave_sample,
O_dout => O_dout => O_wav
); );
end arch; end arch;
#-----------------------------------------------------------
# Vivado v2024.1 (64-bit)
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
# Start of session at: Mon May 5 08:28:17 2025
# Process ID: 6316
# Current directory: /homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum
# Command line: vivado
# Log file: /homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/vivado.log
# Journal file: /homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/vivado.jou
# Running On :fl-tp-br-520
# Platform :Ubuntu
# Operating System :Ubuntu 24.04.2 LTS
# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
# CPU Frequency :4392.091 MHz
# CPU Physical cores:6
# CPU Logical cores :12
# Host memory :16533 MB
# Swap memory :4294 MB
# Total Virtual :20828 MB
# Available Virtual :18868 MB
#-----------------------------------------------------------
start_gui
cd tp-synthe-etudiant-l24beaum/proj
ls
pwd
cd proj
ls
source ./create_project.tcl
update_compile_order -fileset sources_1
launch_simulation
source tb_module_B.tcl
# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
set_property source_mgmt_mode None [current_project]
set_property top tb_module_C [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
# Re-enabling previously disabled source management mode.
set_property source_mgmt_mode All [current_project]
launch_simulation
source tb_module_C.tcl
current_sim simulation_1
close_sim
# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
set_property source_mgmt_mode None [current_project]
set_property top tb_module_D [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
# Re-enabling previously disabled source management mode.
set_property source_mgmt_mode All [current_project]
launch_simulation
source tb_module_D.tcl
# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
set_property source_mgmt_mode None [current_project]
set_property top tb_module_E [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
# Re-enabling previously disabled source management mode.
set_property source_mgmt_mode All [current_project]
launch_simulation
source tb_module_E.tcl
# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
set_property source_mgmt_mode None [current_project]
set_property top tb_module_F [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
# Re-enabling previously disabled source management mode.
set_property source_mgmt_mode All [current_project]
launch_simulation
source tb_module_F.tcl
current_sim simulation_2
close_sim
close_sim
close_sim
# Disabling source management mode. This is to allow the top design properties to be set without GUI intervention.
set_property source_mgmt_mode None [current_project]
set_property top tb_wave_generator [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
# Re-enabling previously disabled source management mode.
set_property source_mgmt_mode All [current_project]
launch_simulation
launch_simulation
launch_runs synth_1 -jobs 6
wait_on_run synth_1
#-----------------------------------------------------------
# Vivado v2024.1 (64-bit)
# SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
# IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
# SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
# Start of session at: Mon May 5 08:28:17 2025
# Process ID: 6316
# Current directory: /homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum
# Command line: vivado
# Log file: /homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/vivado.log
# Journal file: /homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/vivado.jou
# Running On :fl-tp-br-520
# Platform :Ubuntu
# Operating System :Ubuntu 24.04.2 LTS
# Processor Detail :Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz
# CPU Frequency :4392.091 MHz
# CPU Physical cores:6
# CPU Logical cores :12
# Host memory :16533 MB
# Swap memory :4294 MB
# Total Virtual :20828 MB
# Available Virtual :18868 MB
#-----------------------------------------------------------
start_gui
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
cd tp-synthe-etudiant-l24beaum/proj
couldn't change working directory to "tp-synthe-etudiant-l24beaum/proj": no such file or directory
ls
WARNING: [Common 17-259] Unknown Tcl command 'ls' sending command to the OS shell for execution. It is recommended to use 'exec' to send the command to the OS shell.
docs
proj
README.md
src
vivado.jou
vivado.log
vivado_pid6316.str
pwd
/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum
cd proj
ls
WARNING: [Common 17-259] Unknown Tcl command 'ls' sending command to the OS shell for execution. It is recommended to use 'exec' to send the command to the OS shell.
cleanup.cmd
cleanup.sh
create_project.tcl
tb_wave_generator_behav.wcfg
source ./create_project.tcl
# if {[info exists ::create_path]} {
# set dest_dir $::create_path
# } else {
# set dest_dir [pwd]
# }
# puts "INFO: Creating new project in $dest_dir"
INFO: Creating new project in /homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj
# set proj_name "Synthe"
# set origin_dir ".."
# set orig_proj_dir "[file normalize "$origin_dir/proj"]"
# set src_dir $origin_dir/src
# set repo_dir $origin_dir/repo
# set part_num "xc7a200tsbg484-1"
# create_project $proj_name $dest_dir
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/ip'.
create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 8176.906 ; gain = 239.906 ; free physical = 9450 ; free virtual = 16790
# set proj_dir [get_property directory [current_project]]
# set obj [get_projects $proj_name]
# set_property "default_lib" "xil_defaultlib" $obj
# set_property "part" "$part_num" $obj
# set_property "simulator_language" "Mixed" $obj
# set_property "target_language" "VHDL" $obj
# if {[string equal [get_filesets -quiet sources_1] ""]} {
# create_fileset -srcset sources_1
# }
# if {[string equal [get_filesets -quiet constrs_1] ""]} {
# create_fileset -constrset constrs_1
# }
# set obj [get_filesets sources_1]
# set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj
# add_files -quiet [glob -nocomplain ../src/ip/*/*.xci]
# add_files -fileset constrs_1 -quiet $src_dir/constraints
# add_files -quiet $src_dir/hdl
# set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}]
CRITICAL WARNING: [filemgmt 20-1702] Unable to set property on the file: /homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
File is managed as part of sub-design (IP, Block Design, DSP Design, etc.) file: /homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/ip/clk_wiz_0/clk_wiz_0.xci
CRITICAL WARNING: [filemgmt 20-1702] Unable to set property on the file: /homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
File is managed as part of sub-design (IP, Block Design, DSP Design, etc.) file: /homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/ip/clk_wiz_0/clk_wiz_0.xci
# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_wave_generator.vhd]
# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_ADSR_module.vhd]
# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_B.vhd]
# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_C.vhd]
# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_D.vhd]
# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_E.vhd]
# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_F.vhd]
# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_G.vhd]
# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_H.vhd]
# set_property used_in_synthesis false [get_files $src_dir/hdl/tb_module_I.vhd]
# set_property used_in_simulation false [get_files $src_dir/hdl/audioProc.v]
# if {[string equal [get_runs -quiet synth_1] ""]} {
# create_run -name synth_1 -part $part_num -flow {Vivado Synthesis 2014} -strategy "Flow_PerfOptimized_High" -constrset constrs_1
# } else {
# set_property strategy "Flow_PerfOptimized_High" [get_runs synth_1]
# set_property flow "Vivado Synthesis 2014" [get_runs synth_1]
# }
# set obj [get_runs synth_1]
# set_property "part" "$part_num" $obj
# set_property "steps.synth_design.args.fanout_limit" "400" $obj
# set_property "steps.synth_design.args.fsm_extraction" "one_hot" $obj
# set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj
# set_property "steps.synth_design.args.resource_sharing" "off" $obj
# set_property "steps.synth_design.args.no_lc" "1" $obj
# set_property "steps.synth_design.args.shreg_min_size" "5" $obj
# current_run -synthesis [get_runs synth_1]
# if {[string equal [get_runs -quiet impl_1] ""]} {
# create_run -name impl_1 -part $part_num -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
# } else {
# set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
# set_property flow "Vivado Implementation 2014" [get_runs impl_1]
# }
# set obj [get_runs impl_1]
# set_property "part" "$part_num" $obj
# set_property "steps.write_bitstream.args.bin_file" "1" $obj
# current_run -implementation [get_runs impl_1]
# set_property top tb_module_B [get_filesets sim_1]
# set_property top_lib xil_defaultlib [get_filesets sim_1]
# update_compile_order -fileset sources_1
update_compile_order: Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 8240.938 ; gain = 64.031 ; free physical = 9395 ; free virtual = 16751
update_compile_order -fileset sources_1
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'tb_module_B'
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_module_B' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
xvhdl --incr --relax -prj tb_module_B_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_B.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'module_B'
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/tb_module_B.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'tb_module_B'
Waiting for jobs to finish...
No pending jobs, compilation finished.
execute_script: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 8295.117 ; gain = 0.000 ; free physical = 8976 ; free virtual = 16465
INFO: [USF-XSim-69] 'compile' step finished in '6' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_B_behav xil_defaultlib.tb_module_B -log elaborate.log
Vivado Simulator v2024.1
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_B_behav xil_defaultlib.tb_module_B -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package ieee.math_real
Compiling architecture behavioral of entity xil_defaultlib.module_B [module_b_default]
Compiling architecture behavior of entity xil_defaultlib.tb_module_b
Built simulation snapshot tb_module_B_behav
execute_script: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 8295.117 ; gain = 0.000 ; free physical = 8932 ; free virtual = 16486
INFO: [USF-XSim-69] 'elaborate' step finished in '7' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_module_B_behav -key {Behavioral:sim_1:Functional:tb_module_B} -tclbatch {tb_module_B.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
source tb_module_B.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_module_B_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:08 ; elapsed = 00:00:21 . Memory (MB): peak = 8380.371 ; gain = 85.254 ; free physical = 8891 ; free virtual = 16481
set_property top tb_module_C [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/tb_module_C.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/tb_module_C.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/tb_module_C.vhd:]
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'tb_module_C'
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_module_C' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
xvhdl --incr --relax -prj tb_module_C_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_package.vhd" into library xil_defaultlib
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_C.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'module_C'
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/tb_module_C.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'tb_module_C'
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_C_behav xil_defaultlib.tb_module_C -log elaborate.log
Vivado Simulator v2024.1
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_C_behav xil_defaultlib.tb_module_C -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package ieee.math_real
Compiling package xil_defaultlib.wave_package
Compiling architecture behavioral of entity xil_defaultlib.module_C [\module_C(g_n=16)\]
Compiling architecture behavior of entity xil_defaultlib.tb_module_c
Built simulation snapshot tb_module_C_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_module_C_behav -key {Behavioral:sim_1:Functional:tb_module_C} -tclbatch {tb_module_C.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
source tb_module_C.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_module_C_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 8488.684 ; gain = 47.738 ; free physical = 8505 ; free virtual = 16244
current_sim simulation_1
close_sim
INFO: [Simtcl 6-16] Simulation closed
set_property top tb_module_D [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'tb_module_D'
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_module_D' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
xvhdl --incr --relax -prj tb_module_D_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_D.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'module_D'
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/tb_module_D.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'tb_module_D'
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_D_behav xil_defaultlib.tb_module_D -log elaborate.log
Vivado Simulator v2024.1
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_D_behav xil_defaultlib.tb_module_D -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package ieee.math_real
Compiling package xil_defaultlib.wave_package
Compiling architecture behavioral of entity xil_defaultlib.module_D [\module_D(g_n=16)\]
Compiling architecture behavior of entity xil_defaultlib.tb_module_d
Built simulation snapshot tb_module_D_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_module_D_behav -key {Behavioral:sim_1:Functional:tb_module_D} -tclbatch {tb_module_D.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
source tb_module_D.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_module_D_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 8488.684 ; gain = 0.000 ; free physical = 8252 ; free virtual = 16075
set_property top tb_module_E [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'tb_module_E'
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_module_E' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
xvhdl --incr --relax -prj tb_module_E_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_E.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'module_E'
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/tb_module_E.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'tb_module_E'
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_E_behav xil_defaultlib.tb_module_E -log elaborate.log
Vivado Simulator v2024.1
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_E_behav xil_defaultlib.tb_module_E -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package ieee.math_real
Compiling package xil_defaultlib.wave_package
Compiling architecture behavioral of entity xil_defaultlib.module_E [\module_E(g_n=16)\]
Compiling architecture behavior of entity xil_defaultlib.tb_module_e
Built simulation snapshot tb_module_E_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_module_E_behav -key {Behavioral:sim_1:Functional:tb_module_E} -tclbatch {tb_module_E.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
source tb_module_E.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_module_E_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 8558.051 ; gain = 49.742 ; free physical = 8196 ; free virtual = 16021
set_property top tb_module_F [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'tb_module_F'
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_module_F' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
xvhdl --incr --relax -prj tb_module_F_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_F.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'module_F'
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/tb_module_F.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'tb_module_F'
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_F_behav xil_defaultlib.tb_module_F -log elaborate.log
Vivado Simulator v2024.1
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
Running: /usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip -L xpm --snapshot tb_module_F_behav xil_defaultlib.tb_module_F -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling architecture behavioral of entity xil_defaultlib.module_F [\module_F(15,0)(15,0)(15,0)(15,0...]
Compiling architecture behavioral of entity xil_defaultlib.tb_module_f
Built simulation snapshot tb_module_F_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_module_F_behav -key {Behavioral:sim_1:Functional:tb_module_F} -tclbatch {tb_module_F.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Time resolution is 1 ps
source tb_module_F.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_module_F_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 8647.125 ; gain = 70.816 ; free physical = 8184 ; free virtual = 16003
current_sim simulation_2
close_sim
INFO: [Simtcl 6-16] Simulation closed
close_sim
INFO: [Simtcl 6-16] Simulation closed
close_sim
INFO: [Simtcl 6-16] Simulation closed
set_property top tb_wave_generator [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_G.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_A.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_G.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_G.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_G.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_A.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_A.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_A.vhd:]
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'tb_wave_generator'
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_wave_generator' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
xvhdl --incr --relax -prj tb_wave_generator_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_A.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'module_A'
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_G.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'module_G'
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_H.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'module_H'
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_I.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'module_I'
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'wave_generator'
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:67]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:68]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:69]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:70]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:71]
ERROR: [VRFC 10-4982] syntax error near ')' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:73]
ERROR: [VRFC 10-3353] formal port 'i_clk' has no actual or default value [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:62]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:97]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:98]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:99]
ERROR: [VRFC 10-4982] syntax error near ')' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:101]
ERROR: [VRFC 10-3353] formal port 'i_clk' has no actual or default value [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:90]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:111]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:112]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:113]
ERROR: [VRFC 10-4982] syntax error near ')' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:115]
ERROR: [VRFC 10-3353] formal port 'i_clk' has no actual or default value [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:104]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:122]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:123]
INFO: [#UNDEF] Sorry, too many errors..
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-99] Step results log file:'/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim/xvhdl.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim/xvhdl.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-12493] Simulation top is 'tb_wave_generator'
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/usr/home/enstb1/MEE/Xilinx/vivado2024.1/Vivado/2024.1/data/xsim/xsim.ini' copied to run dir:'/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_wave_generator' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim'
xvhdl --incr --relax -prj tb_wave_generator_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_A.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'module_A'
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_G.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'module_G'
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_H.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'module_H'
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/module_I.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'module_I'
INFO: [VRFC 10-163] Analyzing VHDL file "/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'wave_generator'
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:67]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:68]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:69]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:70]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:71]
ERROR: [VRFC 10-4982] syntax error near ')' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:73]
ERROR: [VRFC 10-3353] formal port 'i_clk' has no actual or default value [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:62]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:97]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:98]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:99]
ERROR: [VRFC 10-4982] syntax error near ')' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:101]
ERROR: [VRFC 10-3353] formal port 'i_clk' has no actual or default value [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:90]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:111]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:112]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:113]
ERROR: [VRFC 10-4982] syntax error near ')' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:115]
ERROR: [VRFC 10-3353] formal port 'i_clk' has no actual or default value [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:104]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:122]
ERROR: [VRFC 10-4982] syntax error near ',' [/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/hdl/wave_generator.vhd:123]
INFO: [#UNDEF] Sorry, too many errors..
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim/xvhdl.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.sim/sim_1/behav/xsim/xvhdl.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_runs synth_1 -jobs 6
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: clk_wiz_0
WARNING: [Vivado 12-4801] The synthesis checkpoint for IP '/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/ip/clk_wiz_0/clk_wiz_0.xci' is available but stale and the IP is locked. An out-of-context (OOC) run will be created and/or launched, but synthesis may not be able to complete or could result in incorrect behavior.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead.
WARNING: [Runs 36-337] The following IPs are either missing output products or output products are not up-to-date for Synthesis target. Since these IPs are locked, no update to the output products can be done.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/ip/clk_wiz_0/clk_wiz_0.xci
WARNING: [Runs 36-337] The following IPs are either missing output products or output products are not up-to-date for Implementation target. Since these IPs are locked, no update to the output products can be done.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
/homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/src/ip/clk_wiz_0/clk_wiz_0.xci
[Mon May 5 10:36:04 2025] Launched synth_1...
Run output will be captured here: /homes/l24beaum/Documents/tp_synthe/tp-synthe-etudiant-l24beaum/proj/Synthe.runs/synth_1/runme.log
Source diff could not be displayed: it is too large. Options to address this: view the blob.
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment